The giant processor makers such as Intel and AMD are introducing dual-core and multi-core processors to meet the demanding processing power of the modern applications, since limitations of the current technology and designs prohibit further increase in processor speed.
For better understanding the principle of the present invention, it will be advantageous to give definition to some terms used in the present patent application.
A motherboard, which is also known as the logic board, main board, or computer board, is the computer's main board that holds all CPU, memory, and I/O functions or has expansion slots for them.
A processor core is the processing part of a CPU minus the cache. It is made up of the control unit and the arithmetic logic unit. A multi-core processor is an integrated circuit (IC) to which two or more processors have been attached for enhanced performance, reduced power consumption, and for more efficient simultaneous processing of multiple tasks. A dual-core CPU means that there are two complete execution cores per physical processor. It has two independent processors with dedicated caches and cache controllers onto a single die. One of the applications of dual-core processors is a multitasking environment. Since both cores have access to the front side bus (FSB), operating system (OS) can perform most computational intensive tasks in parallel. Multi-core processor is the extension of dual-core processor where multiple cores are present on the single die instead of only two.
The OS sitting on the server has to support multithreading to take advantage of the dual-core processor. This is one way to boost the system performance by taking advantage of the dual-core technology. Other way of improvement could be if we can dedicate one of the CPU cores to a particular computational intensive application like RAID and leave the other for running the OS with the user applications. This looks like an ideal situation for a multiple processor, because today the RAID application is almost a separate OS running on an I/O processor with its own resources.
The RAID, which is deciphered as Redundant Array of Independent Disks, i.e., as a disk subsystem that is used to increase performance or provide fault tolerance or both. RAID uses two or more ordinary hard disks and a RAID disk controller. RAID subsystems come in all sizes from desktop units to floor-standing models. Stand-alone units may include large amounts of caches as well as redundant power supplies. Initially used with servers, desktop PCs are increasingly being retrofitted by adding a RAID controller and extra SATA or Serial ATA (Advanced Technology Attachment) or SCSI (Small Computer System Interface, pronounced “skuzzy”) disks. Newer motherboards often have RAID controllers.
A typical conventional multi-core CPU which consists of two or more processors put together on a single die which shares the same inter connect to the rest of the system is called a Multi-core CPU. Each core by itself has its own L1, L2 caches and may independently implement superscalar execution, pipelining, and multithreading.
Interconnection between two or more buses with different speeds and bandwidths on a motherboard is achieved using special controllers called bridges. A conventional multi-core system normally consists of a dual core CPU, North Bridge and South Bridge. The CPU is the heart of the computer motherboard. The data transfer between the CPU and other components like RAM (Random Access Memory), hard disk, etc., on the motherboard is performed via buses. Based on the amount of data that is to be handled by each component on the motherboard, there may be several buses on the motherboard.
The bus that is nearest to the CPU is the fastest bus known as the Front Side Bus (FSB), which connects RAM and CPU. The buses connecting the I/O devices are the slower buses. All the controllers connected to the fast buses are grouped together and put as one large chip that constitutes the aforementioned North Bridge, while the controllers connected to the slow buses are grouped together to make a large chip that constitutes the aforementioned South Bridge. The North Bridge and South Bridge together are called Chip set.
The basic function of the aforementioned RAID controller is to provide connectivity between a host computer and storage devices such as, e.g., hard disks. There are many ways in which RAID stack can be implemented.
Given below are several examples of use of RAID stacks, where only those elements and units that are essential for understanding the invention will be shown in the drawings and designated by reference numerals.
1) Hardware RAID Controller
This is the one of the best RAID solutions available in the market today. A data-exchange diagram of a hardware design of the I/O processor-based RAID controller that is used in the aforementioned product is shown in FIG. 1. As can be seen from FIG. 1, the I/O processor-based RAID controller, which as a whole is designated by reference numeral 20 consists of the following components: an I/O processor 22, which is connected to a DDRII (the abbreviation for Double Data Rate Two), a DDRII 25 which is a high-speed variant of synchronous dynamic random access memory (SDRAM) that is used in personal computers as well as in many other intelligent electronic devices) (not shown), a SAS (Serial Attached SCSI) protocol specific chip 24 to which the I/O processor 22 is connected through a PCI-X (Peripheral Component Interconnect Extended) bus 23, as well as a flash chip 26 and NVRAM (Non-Volatile Random Access Memory) 28 which are also connected to the I/O processor through the local bus 27.
Other components shown in FIG. 1 are the following: a PCI Express Interface linked to the I/O Processor 22 via PCIEx8 designated by reference numeral 29, battery backup 30 linked to the I/O Processor 22 via GPIOs (General Purpose Inputs/Outputs), etc.
2) RAID on Mother Board (ROMB):
The ROMB is good with respect to cost and performance but involves the same special hardware on the motherboard, like I/O processor, flash chip, NVRAM, special DDR circuitry, battery back up module etc.
3) RAID on Chip (ROC)
This solution is similar to Hardware solution except it uses a special chip that has both I/O processor and the backend device (SCSI/SAS/SATA) integrated into a single chip.
4) Software RAID
Software RAID is a RAID stack running as a driver. This approach is practical due to the fast processor that exists today in the market. But the disadvantage is that it consumes a significant part of the system resources and delays operation of the OS and thus impairs the performance of the system.
5) RAID on File System
A great number of file systems already implement RAID but do not have an opportunity of using key features of RAID subsystems such as Rebuild, RAID Level Migration (RLM), Online Capacity Expansion (OCE), Back Ground Initialization (BGI), Check Consistency, Enclosure Management, etc.
6) RAID on Virtual Machine (VM)
A Virtual Machine (VM) is a software implementation of a machine (computer) that executes programs like a real machine, using underlying hardware API's (where API is Application Program Interface) provided by the hardware of the virtual machine. In a multiple core environment, the RAID can be run on a Virtual Machine. But this approach of RAID implementation also incorporates delays in many API layers and queue delays of the multiple OS running on the multiple cores. Hence it hampers the total performance of the RAID subsystem, and may lead to other complications dealing with specific features of the OS.
Given below are some examples illustrating independent use of RAID and multi-core processors in computer systems.
US Patent Application Publication No. 20070239932 published in 2007 (inventor V. Zimmer, et al.) discloses a method that includes partitioning a plurality of core processors into a main partition comprising at least one processor core capable of executing an operating system and an embedded partition comprising at least one different processor core. The main partition and embedded partition may communicate with each other through a bridge. The embedded partition of this embodiment may be capable of: mapping two or more mass storage systems, coupled to the embedded partition, into a single logical device; presenting the logical device to the bridge; and receiving at least one I/O request, generated by the main partition and directed to the logical device, and in response to the I/O request, the embedded partition may be further capable of communicating with at least one of the two or more mass storage systems using at least one communication protocol to process said I/O request; and reporting the status of the I/O request to the main partition, via the bridge.
US Patent Application Publication No. 20070185942 published in 2007 (inventor Hitz, David) discloses an Allocating files in a file system integrated with a RAID disk sub-system. Integrating a file system with a RAID array that exports precise information about the arrangement of data blocks in the RAID subsystem. The invention uses separate current-write location (CWL) pointers for each disk in the disk array where the pointers simply advance through the disks as writes occur. The invention writes on the disk with the lowest CWL pointer. A new disk is chosen only when the algorithm starts allocating space for a new file, or when it has allocated N blocks on the same disk for a single file. A sufficient number of blocks are defined as all the buffers in a chunk of N sequential buffers in a file. The result is that CWL pointers are never more than N blocks apart on different disks, and large files have N consecutive blocks on the same disk.
US Patent Application Publication No. 20070168399 published in 2007 (inventor Schultz, Thomas) discloses an Exposed sequestered partition apparatus, systems, and methods. Apparatus, systems, methods, and articles may operate to store one or more parameters associated with a pseudo-device in a device configuration table associated with a first partition within a multi-partition computing platform. An inter-partition bridge (IPB) may be exposed to an operating system executing within the first partition. The IPB may be adapted to couple the first partition to a second partition sequestered from the first partition. The IPB may be configured by the parameter(s) associated with the pseudo-device. Other embodiments may be described and claimed.
U.S. Pat. No. 6,549,980 published in 2003 (inventor Landau, Richard B.) discloses a Manufacturing process for software for software raid disk sets in a computer system. A method of manufacturing a computer includes creating a reference two-disk software RAID pair, the software RAID pair having desired partitions mirrored by an operating system. The method also includes extracting a master image from one disk of the reference disk pair, performing a difference comparison of partitions of a target disk of the reference disk pair against the master image and obtaining a collection of differences. The method further includes writing the master image to each disk of a disk set in the computer being manufactured and applying the collection of differences to a target disk of the disk set.
U.S. Pat. No. 6,904,497 published in 2005 (inventor Beckett, Peter H) discloses a Method and apparatus for extending storage functionality at the bios level. A method and apparatus for implementing RAID through control of the IO channels on the motherboard is provided. One exemplary method locates IO channels on a motherboard. Next, the IO channels on the motherboard are controlled where the IO channels are configured to communicate with a storage media. Then the storage media associated with the IO channels is managed as a RAID. Some notable advantages of the discussed methods and apparatuses include the simplicity of implementing the host based RAID through existing infrastructure contained within a computing system. Additionally, the added benefits of improving reliability and system performance associated with a RAID subsystem are made available in a cost effective manner because most of already existing infrastructure.
U.S. Pat. No. 6,065,096 published in 2000 (inventor Brian A. day) discloses an Integrated single chip dual mode raid controller. A RAID controller integrated into a single chip. The RAID controller chip includes a general purpose RISC processor, memory interface logic, a host CPU PCI bus, at least one back-end I/O interface channel, at least one direct memory access (DMA) channel, and a RAID parity assist (RPA) circuit. The RAID chip enables higher integration of RAID functions within a printed circuit board and in particular enables RAID function integration directly on a personal computer or workstation motherboard. The back-end I/O interface channel is preferably dual SCSI channels. The RAID chip is operable in either of two modes. In a first mode, the chip provides pass through from the host CPU interface directly to the dual SCSI channels.
This first mode of operation, a SCSI pass-through mode, allows use of the chip for non-RAID storage applications and enables low level manipulation of the disk array in RAID applications of the chip. The first mode of operation permits use of the chip without change to host applications and drivers. Rather, the chip is operable in a manner compatible with known available SCSI controller devices. The second mode of operation, a RAID control mode, provides full RAID management features to the attached host CPU. In the preferred embodiment, the RAID chip presents an Intelligent I/O (I2O) interface to the host CPU to enhance portability and performance of the host/RAID interaction.
Generally, redundancy in data processing apparatuses has been used to improve fault tolerance, reliability, and manufacturing yield. Computers have been built with redundant elements, such as data storage disks, to prevent the loss of data in the event of a hardware failure. Computers have also been built with redundant elements, such as processor chips, to provide for automatic replacement of an element that fails during use, or to provide for error detection by executing instructions in “lockstep,” meaning that instructions are executed redundantly. Computer chips including circuitry that may be arranged as arrays, such as memories, have been built with redundant columns that may be used to replace columns that include manufacturing defects or fail as a result of use. However, the use of redundancy within processor chips has been limited by the dense, irregular nature of the transistor layout in processors. An attempt to solve the above problem is described in US Patent Application Publication No. 20060212677 published in 2006 (inventor T. Fossum). The publication describes embodiments of a multi-core processor having active and inactive execution cores. In one embodiment, an apparatus includes a processor having a plurality of execution cores on a single integrated circuit, and a plurality of core identification registers. Each of the plurality of core identification registers corresponds to one of the execution cores to identify whether the execution core is active.
However, as has been mentioned above, all the above implementations are either expensive solution where they need specialized hardware or some of them adversely affect the I/O performance where the RAID operation is done in software. More specifically, in order to improve I/O performance, the system may require expensive solutions such as hardware RAID controllers. None of the above inventions has the inexpensive solution of using one of the independent cores of the main multi-core CPU which is the heart of the computer system for RAID processing and this processing power is always available in present day computer systems with multi-core CPU.
Above we have described various implementations of the RAID solution, showed that the I/O processor is a main component of a hardware RAID controller and that the existing RAID solutions have disadvantages. It also should be noted that the above-mentioned known multi-core processors, e.g., a dual-core processors, also suffer from a number of disadvantages, one of which is that they are not used to their full potentials so that a part of their capacities remains unused for other possible applications.